/**********************************************************************************
 *@file    : sys_watchdog.c 
 *@brief   : 看门狗驱动
 *@author  : mcu
 *@version : Ver 1.1
 *@data    : 2018-03-23
 *@note    : Copyright(c) 2018 JJI. All rights reserved.
 ***********************************************************************************/
 
#include "mid_watchdog.h"
#include "ac780x_wdg_reg.h"

// //在初始化上电之后， system_S32K144.c -> void SystemInit(void) 里面初始化了看门狗（disable）
// //默认时钟源为LPO，即128K频率驱动
// //1024个周期之后，即8s之后就会复位，因此为了避免这个条件，需要在到达1024个循环之前就对看门狗进行配置。
// //在复位之后，看门狗是默认开启的
// void wdog_start(uint32_t timeout)
// {
// 	uint32_t cs = WDOG->CS;
// 	DisableInterrupts;
// 	cs &= ~(WDOG_CS_WIN_MASK | WDOG_CS_PRES_MASK | WDOG_CS_CLK_MASK | WDOG_CS_INT_MASK |
// 			WDOG_CS_UPDATE_MASK | WDOG_CS_DBG_MASK | WDOG_CS_WAIT_MASK | WDOG_CS_STOP_MASK);
// 	cs |= WDOG_CS_PRES(1); /* WDOG prescaler             */
// 	cs |= WDOG_CS_CLK(1); /* WDOG clock source */
// 	cs |= WDOG_CS_UPDATE(1); /* Enable/Disable further updates of the WDOG configuration */
// 	cs |= WDOG_CS_FLG_MASK; /* Reset interrupt flags */
// 	cs |= WDOG_CS_EN_MASK | WDOG_CS_CMD32EN_MASK; /* Enable WDOG in 32-bit mode */

// 	WDOG->CNT = 0xD928C520UL; //解锁
// 	while(((WDOG->CS & WDOG_CS_ULK_MASK) >> WDOG_CS_ULK_SHIFT) == 0U); /* Wait until registers are unlocked */
// 	WDOG->CS = cs;
// 	WDOG->TOVAL = timeout;
// 	while(((WDOG->CS & WDOG_CS_ULK_MASK) >> WDOG_CS_ULK_SHIFT) == 1U); /* Wait until the unlock window closes */
// 	while(((WDOG->CS & WDOG_CS_RCS_MASK) >> WDOG_CS_RCS_SHIFT) == 0U); /* Wait until the reconfiguration successful */
// 	EnableInterrupts;
	
// }

// void wdog_feed(void)
// {
// 	DisableInterrupts;     //关总中断
// 	WDOG->CNT = 0xB480A602UL; //喂狗
// 	EnableInterrupts;      //开总中断
// }

// void wdog_stop_by_toval(void)
// {
// 	//停止看门狗，通过增大溢出值的方式
// 	uint32_t cs = WDOG->CS;
// 	cs |= WDOG_CS_UPDATE(1); /* Enable/Disable further updates of the WDOG configuration */
// 	WDOG->CNT = 0xD928C520UL; //解锁
// 	while(((WDOG->CS & WDOG_CS_ULK_MASK) >> WDOG_CS_ULK_SHIFT) == 0U); /* Wait until registers are unlocked */
// 	WDOG->CS = cs;
// 	WDOG->TOVAL = 0xffffffff;
// 	while(((WDOG->CS & WDOG_CS_ULK_MASK) >> WDOG_CS_ULK_SHIFT) == 1U); /* Wait until the unlock window closes */
// 	while(((WDOG->CS & WDOG_CS_RCS_MASK) >> WDOG_CS_RCS_SHIFT) == 0U); /* Wait until the reconfiguration successful */
// 	EnableInterrupts;
// }
// void wdog_stop(void)
// {
// 	// DisableInterrupts;           //关总中断
// 	// WDOG->CNT = 0xD928C520UL;       //解锁
// 	// WDOG->CS &= ~WDOG_CS_EN_MASK; //关闭开门狗
// 	// WDOG->TOVAL=0x0000FFFFUL;	/* Maximum timeout value */  
// 	// EnableInterrupts;            //开总中断


// 	DisableInterrupts;

//     /* If allowed reconfigures WDOG */
//     if (((WDOG->CS & WDOG_CS_UPDATE_MASK) >> WDOG_CS_UPDATE_SHIFT) != 0U)
//     {
//         /* Disable WDOG timeout interrupt */
// 		NVIC_DisableIRQ(WDOG_EWM_IRQn);
//     }
// 	 /* Unlock WDOG register */
//     WDOG->CNT = 0xD928C520UL;
//     /* Disable WDOG, enables support for 32-bit refresh/unlock command, LPO clock source,
//        allow updates and disable watchdog interrupts, window mode, wait/debug/stop mode */
//     WDOG->CS    = 0x2520U;
//     /* Default timeout value */
//     WDOG->TOVAL = FEATURE_WDOG_TO_RESET_VALUE;
//     /* Clear window value */
//     WDOG->WIN   = FEATURE_WDOG_WIN_RESET_VALUE;

//     /* Refresh counter value */
//     if ((WDOG->CS & WDOG_CS_CMD32EN_MASK) != 0U)
//     {
//         WDOG->CNT = FEATURE_WDOG_TRIGGER_VALUE;
//     }
//     else
//     {
//         WDOG->CNT = FEATURE_WDOG_TRIGGER16_FIRST_VALUE;
//         (void)WDOG->CNT;
//         WDOG->CNT = FEATURE_WDOG_TRIGGER16_SECOND_VALUE;
//     }

//     while(((WDOG->CS & WDOG_CS_RCS_MASK) >> WDOG_CS_RCS_SHIFT) == 0U); /* Wait until the reconfiguration successful */
//     /* Enable global interrupt */
//     EnableInterrupts;
// }

void mid_watchdog_init(void)
{
    WDG_ConfigType wdg_config;
    memset(&wdg_config, 0U, sizeof(wdg_config));

    wdg_config.clockSource  = WDG_CLOCK_LSI;    /* Select WDG clock source: LSI32K */
    wdg_config.prescalerEn  = DISABLE;          /* Disable WDG fixed 256 prescaler */
    wdg_config.timeoutValue = 159999;           /* WDG timeout value, timeout time = (159999 + 1) / 32000 = 5s(clock source is LSI32K) */
    wdg_config.windowValue  = 0U;               /* WDG window timeout value */
    wdg_config.updateEn     = ENABLE;           /* Enable WDG update, if update is 0, can't set WDG register */
    wdg_config.WDGEn        = ENABLE;           /* Enable WDG */
    wdg_config.interruptEn  = DISABLE;          /* Disable WDG interrupt */
    wdg_config.windowEn     = DISABLE;          /* Disable WDG window mode */
    wdg_config.callBack     = NULL;             /* WDG Callback function */

    /* WDG Init */
    WDG_Init(&wdg_config);

    /* Refresh WDG */
    WDG_Feed();
}

void mid_watchdog_deinit(void)
{
	WDG_DeInit();
}


void mid_watchdog_feeddog(void)
{
	WDG_Feed();
}

uint32_t get_watchdog_Cnt(void)
{
    return WDG_GetTimeoutCnt();
}

// void mid_watchdog_stop(void)
// {
// 	wdog_stop_by_toval();
// }
